1. Field of Invention
The present invention relates generally to signal controlled phase shifters and more particularly to a phase shifter including at least several delay elements having connections to an output terminal controlled in response to the value of a control signal.
The invention is also related to a signal multiplexer responsive to at least several signals and more particularly to such a multiplexer which is responsive to a reflected coded signal.
2. Description of the Related Art
Signal controlled phase shifters are usually analog devices including a variable reactance, such as a varactor, having a value controlled by the amplitude of a voltage. Such phase shifters are frequently employed in voltage controlled variable frequency oscillators, such as are employed in phase locked loops. In such applications, a fixed clock is supplied to the voltage controlled, variable frequency oscillator to derive an output frequency that is fed back to one input of a phase detector, having a second input responsive to an input frequency. The phase detector derives an error voltage that is fed to a loop filter which supplies the voltage controlled oscillator with a variable amplitude voltage for controlling the oscillator output frequency. Phase locked loops are used to lock a receiver to an incoming frequency with zero frequency or phase error. In receivers responsive to variable phase signals representing digital data, e.g. QPSK or BPSK signals, a demodulator of the receiver is locked to a symbol frequency with zero phase error. Such locking is usually performed with a first or second order phase locked loop.
The prior art analog phase shifters and analog based phase locked loops have the usual disadvantages associated with analog circuitry, i.e., lack of repetitiveness in manufacturing and performance unless "tweaking" procedures are used, low yield production, inaccuracy and the need to adapt the analog circuitry to the remaining parts of the equipment. To overcome these problems, digitally based phase locked loops have been developed. One digitally based phase locked loop responsive to base band signals to be demodulated includes an analog-to-digital converter having one input responsive to such a signal. The converter has a second input responsive to a sampling clock having a variable frequency controlled by the digital phase locked loop. The converter derives a multi-bit digital output signal having a variable value dependent on the amplitude of the base band signal when a sample derived by the clock occurs. The base band signal is subject to a full gamut of amplitude variations because of imperfections in the transmission and processing of the signal between the origination site and the phase locked loop site. Normally at least two samples of the variable phase signal are taken during each symbol.
The variable digital output signal of the converter is supplied to a symbol data decoder and error generator. The symbol data decoder and error generator derives a data output signal representing the digital value of the symbol, as well as a signal indicative of the phase error between the variable phase signal and the sampling clock. The phase error digital control signal is supplied to a symbol timing loop filter, which in turn drives a direct digital synthesizer, having a digital output signal with values representing the amplitude of a sine wave. The direct digital synthesizer drives a digital to analog converter, having a sinusoidal-like output with values equal to the digital values derived by the synthesizer. The digital to analog converter sinusoidal-like output is supplied to a lowpass filter. Direct digital synthesizers are frequency limited to a few megaHertz, so the lowpass filter output is considerably lower in frequency than the base band signal supplied to the analog-to-digital converter. To provide the analog-to-digital converter with an acceptable sampling frequency, the lowpass filter output is supplied to a frequency multiplying phase locked loop. Hence, this prior art system is relatively complex, requiring an analog phase locked loop within the digital phase locked loop, as well as a digital to analog converter and a lowpass filter.
Another prior art digitally based system for demodulating variable phase intelligence signals supplied to a receiver includes an analog-to-digital converter having first and second inputs respectively responsive to the base band signal and a fixed frequency sampling clock. The analog-to-digital converter derives a digital output having values indicative of the amplitude of the base band signal supplied to the converter at the time each sampling clock occurs. To determine the precise level of the analog-to-digital converter output signal, an interpolator responds to the converter output to find the sampled values at the desired time. The interpolator is either of the finite or infinite impulse response type. The interpolator derives a digital output which is supplied to a symbol timing processor having an output which updates coefficients used in the interpolator. The symbol timing processor also derives data representing output signals.
One further type of digitally based phase locked loop samples the amplitude of a received signal. The resulting samples are processed to derive an error control signal for the frequency of the sampling source. The error control signal controls the frequency of the sampling source by selecting one of several predetermined frequency division factors for a fixed clock source. As the error changes, the frequency division factor changes, to vary the sampling source frequency by discrete, fixed amounts. This type of phase lock loop has the disadvantage of not being suitable for high frequency sampling sources and does not provide high frequency resolution.
It is, accordingly, an object of the present invention to provide a new and improved signal controlled phase shifting apparatus and method.
Another object of the present invention is to provide a new and improved signal controlled variable frequency oscillator and to provide a method of deriving a variable frequency wave in response to a control signal.
An additional object of the invention is to provide a new and improved digitally based phase locked loop and a method of digitally phase locking an input frequency and a clock.
Still another object of the invention is to provide a digitally based phase locked loop including a digitally controlled asynchronous phase shifter responsive to a fixed frequency clock.
A further object of the present invention is to provide a digitally based phase locked loop suitable for high frequencies that is relatively inexpensive because it employs a fixed frequency oscillator reference.